This invention relates to clock data recovery (CDR) applications. More particularly, this invention relates to a Bang-Bang CDR loop with a separate proportional path to improve loop stability.
It is almost axiomatic that digital systems are clocked. When sampling data in a digital system, it is important to have an accurate clock, so that the sampling can occur as close as possible to the center of the data eye for accurate reading of the data. This is relatively easy when the clock is sent along with the data. However, when the clock must be recovered from the data, clock recovery errors could make centering the sampling time in the data eye difficult or unreliable. Any such problems are compounded in a programmable logic device, where the circuit paths, as well as the clock recovery circuitry, differ from one user logic design to the next.
Clock recovery is commonly accomplished using a loop circuit—i.e., a phase-locked loop (PLL) or delay-locked loop (DLL)—in which a phase detector detects a phase variation between input and recovered signals, causing a charge pump to vary a control signal (i.e., voltage or current) of an oscillator or delay line (e.g., a voltage-controlled oscillator or current-controlled oscillator) to bring the recovered signal back into alignment with the input signal. Variation or ripple in the control signal may cause unacceptable jitter in the oscillator output, giving rise to clock recovery errors, which in turn result in data read errors.
One type of phase detector for a CDR loop is a nonlinear phase detector known as a Bang-Bang phase detector. When a Bang-Bang phase detector is used in a CDR loop circuit, the loop stability may be affected, particularly at high frequencies, by parasitic or other capacitance in parallel with the loop filter, which may give rise to third-order effects.
It would be desirable to be able to provide a Bang-Bang CDR loop with increased stability.